This invention relates to methods of manufacture of vertical transistors in DRAM and eDRAM devices and more particularly to methods for providing devices with reduced parasitic capacitance while employing an economical manufacturing process.
The vertical transistor DRAM/embedded DRAM allows us to use a line shaped mask to contact the bitline junction of the array as demonstrated by commonly assigned U.S. Pat. No. 6,245,651 of Divakaruni et al. for Method of Simultaneously Forming a Line Interconnect and a Borderless Contact to Diffusion. Lines are simpler to print and improve process yield. For DRAM with borderless contacts, the line contact mask increases the bitline capacitance and compromises performance. Hence, there is a need to make contacts only on one side of the wordlines (gate conductors).
Consequently, methods have been shown to allow one single borderless while still using a line shaped mask as shown by commonly assigned, copending U.S. patent application Ser. No. 10/026,119 filed on Dec. 21, 2001 of Divakaruni and Radens for DRAM Array Bit Contact with Relaxed Pitch Pattern. However, the variation of the gate conductor over the trench due to standard process variation is limited by the thickness of the spacer on the inside of the trench. This places a rather severe constraint on the overlay conditions for the printing of the wordline (gate conductor). The present invention provides a solution to this problem by using asymmetric spacers in the trench. By making the spacers asymmetric (or existing on only one side), the overlay constraints are greatly relaxed.
See U. Gruening, A Novel Trench DRAM Cell with a Vertical Access Transistor and Buried Strap (VERI BEST) for 4 Gb/ 16 Gb, IEDM Tech. Digest, pp. 2529 (1999).
Also see S. Wuensche, A 110 nm 512 Mb DDR DRAM with Vertical Transistor Trench Cell. 2002 Symposium on Circuits Digest of Technical Papers, IEEE, pages 114-115 (2002).
In the current state of the art, 110 nm generation vertical transistor DRAM devices require one bitline contact per cell to reduce bitline parasitic capacitance to meet high speed specifications, such as a Double Data Rate II (DDRxe2x80x94II) DRAM type of device.
The state of the art has been to employ a 193 nm single contact mask to form the bitline contact. However, the cost of the 193 nm mask and the required equipment to perform the required photolithography is very high. Moreover, for that purpose the Deep Trench (DT) has to be shifted to one side to prevent a short circuits between the DT polysilicon (Deep Trench polysilicon) and the bitline contact which is a problem because it complicates the integration process and has an adverse impact on product yield because of excessive short circuits.
In accordance with this invention a one-side spacer is provided to prevent short circuits between the bitline contact and vertical gate polysilicon. The advantage of the provision of the one-side spacer improves photomask misalignment tolerance for higher product yields.
Another advantage of the present invention is that a 248 nm mask is used which is much more economical than the 193 nm photomask employed in the industry currently as the state of the art practice.
The method of this invention makes it possible to form a single Bitline Contact (BC) using more mature 248 nm masks to reduce cost and to improve photomask misalignment tolerance.
The method of this invention makes it possible to form a unique pattern for a bitline contact VIA in DRAM/e-DRAM devices using a mature generation of photolithography technology to reduce cost and improve yield.
A unique pattern of inside spacers (using older generation lithography technology) are formed in the deep trench of the vertical gate transistor DRAM/e-DRAM array to prevent shorts between the wordlines and the bitlines.
A dual damascene process is used to form the bitline contact via and to form bitlines.
In accordance with this invention, a method is provided form forming a bitline contact in an integrated circuit structure, including a substrate with a top surface and a body, a plurality of deep trenches formed in the body with upper and lower sidewalls, with a deep trench capacitor and a gate electrode formed in the deep trenches, the gate electrodes being separated from the body by gate oxide and the deep trench capacitors being separated from the body by capacitor dielectric layers; a doped source region juxtaposed with the gate electrodes near the top surface aside from the gate oxide; and drain regions formed in the body of the substrate connected to the capacitor, with sidewall spacers between the gate electrodes and the upper sidewalls of the deep trench. The method comprises te following steps. Form a patterning mask over the device exposing a portion of an upper surface of a gate electrode at the top surface of the substrate, the patterning mask being patterned by the line shaping master mask. Etch a divot reaching down into the gate electrode alongside a deep trench sidewall spacer juxtaposed with a source region. Fill the divot with a dielectric material. Form a wordline stack with a wordline and a silicon nitride cap in contact with the gate electrode. Form a conformal liner which is etch resistant covering the structure. Form a planarized ILD layer covering the conformal liner. Form a glass layer covering the planarized glass layer. Form a bitline contact mask patterned by the line shaping master mask, with a bitline contact therethrough above the source region juxtaposed with the deep trench sidewall spacer. Etch a via hole down to the source region in the pattern of the bitline contact mask and form a bitline contact in the via hole.
Preferably, the divot is filled with silicon nitride by depositing a thick layer thereof followed by planarization , and the etch resistant liner comprises a conformal layer of silicon nitride.
Preferably, the bitline contact mask has been formed over an MO wiring line hard mask and the bitline contact mask is employed to etch an opening through a line in an MO hard mask through the dielectric layer therebelow including a portion of the liner covering the wordline with an etchant selective to the hard mask and then remove the bitline contact mask and etching selective to the etch resistant liner.
Preferably, the bitline contact mask has an opening projecting at right angles in the horizontal plane relative to the opening in the MO hard mask. Preferably, the ILD layer is a BSPG layer which is next planarized by CMP and then covered in turn by a TEOS glass layer.